From 0163e828acc638c08b3f760d533b91aba85004ea Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Thu, 18 Jul 2024 10:52:52 -0400 Subject: [PATCH 1/2] zdb: Fix printf formatting of a uint64_t This fixes the build on 32-bit platforms. Fixes: dc91e7452482 ("zdb: dump ZAP_FLAG_UINT64_KEY ZAPs properly (#16334)") --- sys/contrib/subrepo-openzfs/cmd/zdb/zdb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/contrib/subrepo-openzfs/cmd/zdb/zdb.c b/sys/contrib/subrepo-openzfs/cmd/zdb/zdb.c index 11349ba8bf1c..9dbae0168e5d 100644 --- a/sys/contrib/subrepo-openzfs/cmd/zdb/zdb.c +++ b/sys/contrib/subrepo-openzfs/cmd/zdb/zdb.c @@ -1131,8 +1131,8 @@ dump_zap(objset_t *os, uint64_t object, void *data, size_t size) !!(zap_getflags(zc.zc_zap) & ZAP_FLAG_UINT64_KEY); if (key64) - (void) printf("\t\t0x%010lx = ", - *(uint64_t *)attr.za_name); + (void) printf("\t\t0x%010llx = ", + (u_longlong_t)*(uint64_t *)attr.za_name); else (void) printf("\t\t%s = ", attr.za_name); From 95e3175015ae1fba5206c0a32a80afca43558968 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Fri, 10 Jan 2025 17:57:19 -0500 Subject: [PATCH 2/2] riscv atomic.h: Use __ATOMIC_RELAXED for the cmpset_rel fail memory order __ATOMIC_RELEASE is not permitted as a fail memory order and LLVM 18 errors on this. --- sys/riscv/include/atomic.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/sys/riscv/include/atomic.h b/sys/riscv/include/atomic.h index 3aab8c19272c..2d2c7db08da1 100644 --- a/sys/riscv/include/atomic.h +++ b/sys/riscv/include/atomic.h @@ -63,7 +63,7 @@ atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ atomic_##NAME##_##WIDTH(p, v); \ } -#define ATOMIC_CMPSET_ORDER(WIDTH, SUFFIX, ORDER) \ +#define ATOMIC_CMPSET_ORDER(WIDTH, SUFFIX, SUCCESS, FAIL) \ static __inline int \ atomic_cmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ uint##WIDTH##_t cmpval, uint##WIDTH##_t newval) \ @@ -71,10 +71,10 @@ atomic_cmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ \ /* Return 1 on success, 0 on failure */ \ return (__atomic_compare_exchange_n( \ - p, &cmpval, newval, 0, ORDER, ORDER)); \ + p, &cmpval, newval, 0, SUCCESS, FAIL)); \ } -#define ATOMIC_FCMPSET_ORDER(WIDTH, SUFFIX, ORDER) \ +#define ATOMIC_FCMPSET_ORDER(WIDTH, SUFFIX, SUCCESS, FAIL) \ static __inline int \ atomic_fcmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ uint##WIDTH##_t* cmpval, uint##WIDTH##_t newval) \ @@ -82,24 +82,24 @@ atomic_fcmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ \ /* fcmpset updates cmpval on failure and uses weak cmpxchg */ \ return (__atomic_compare_exchange_n( \ - p, cmpval, newval, 1, ORDER, ORDER)); \ + p, cmpval, newval, 1, SUCCESS, FAIL)); \ } #define ATOMIC_CMPSET_ACQ_REL(WIDTH) \ - ATOMIC_CMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE) \ - ATOMIC_CMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE) + ATOMIC_CMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE) \ + ATOMIC_CMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE, __ATOMIC_RELAXED) #define ATOMIC_CMPSET(WIDTH) \ - ATOMIC_CMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED) \ + ATOMIC_CMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED, __ATOMIC_RELAXED) \ ATOMIC_CMPSET_ACQ_REL(WIDTH) #define ATOMIC_FCMPSET_ACQ_REL(WIDTH) \ - ATOMIC_FCMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE) \ - ATOMIC_FCMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE) + ATOMIC_FCMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE) \ + ATOMIC_FCMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE, __ATOMIC_RELAXED) #define ATOMIC_FCMPSET(WIDTH) \ - ATOMIC_FCMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED) \ + ATOMIC_FCMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED, __ATOMIC_RELAXED) \ ATOMIC_FCMPSET_ACQ_REL(WIDTH) \ #ifdef __CHERI_PURE_CAPABILITY__