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How to implement the Fault Escalation Mechanism #54
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Hi, you are correct that there is no lockup state support at all. There is some level of exception support (see especially "impl ExceptionHandling for Processor" in exception.rs). It tries to follow the ARM reference manuals for different kinds of exceptions but like you noticed, things are missing still. The way the exception handing is done:
To actually implement lockup-state, we should first investigate all of it from the ARM v6m and ARM v7m ref manuals. It seems that there is both centralized and spread-out bits and hints how the lockup state should work. In ARM v7m ref manual, chapter B1.5.15 Unrecoverable exception cases seems to have the main implementation information. Searching "lockup" gives hits in many places of the manual. The way I read the definition: when in lockup state, the simulator should keep on executing same instruction from a fixed address. Also the simulator should signal outside the simulation that the processor is in lockup state. Then based on the implementation / use case (eg driven by GDB, or the cli + trace or even a GUI in the future) the implementation can choose how to react to lockup-state. The reaction to lockup state could be even a configurable parameter in the CLI (exit on lockup, keep on executing). It also seems that the processor can actually exit the lockup state via NMI, reset, debug agent or special case like memory error resolving. for example it should be possible to stop the execution via debugger and correct the registers, including PC and continue execution. |
Thanks for the detailed explanation and pointers! I’ve also gone through the ARMv6-M and ARMv7-M reference manuals, especially section B1.5.15, which lays out the unrecoverable exception cases pretty clearly. It mentions that when a supervisory call or fault happens at priority -1 or higher, like in the hard fault handler, the lockup mechanism is supposed to kick in. In the lockup state, the processor keeps executing from the PC address Apparently, the processor can only recover from lockup via NMI if the lockup happened at priority -1, which means during a hard fault. To handle lockup, my thought is to add a |
That sounds reasonable way to implement this. The code running the simulation can then check the lockup variable and react to that if needed. It would be great if the implementation could also include a test case for this in one form or another. |
I have a question though. does get_execution_priority() return the current execution priority? In case of a hard fault, i would expect it to return -1, but it returns 0. Is this as expected, or is a bug? |
The get_execution_priority() tries to implement the pseudocode function "integer ExecutionPriority()" from ARM V7M (and V6M) reference manuals. As you can see, there are several things that have an effect for the output value of the function. Can you list the conditions that you have and compare them to the pseudocode function? Maybe this helps to reason about the possibility of the bug. |
Hi,
I was running a program inside the simulator, that triggers a HardFault inside the HardFault handler code. This caused the simulator to enter an infinite loop, where a HardFault continuously triggers another HardFault, and so on until it breaks.
From the ARMv6-M architecture manual:
The standard exception entry mechanism does not apply where a fault or Supervisor Call occurs at a priority of -1 or higher.
It seems the simulator does not implement this Lockup behavior, the current behavior leads to the infinite loop described above.
Could you clarify how the fault escalation mechanism is intended to work in the simulator? Additionally, do you think the behavior should be adjusted to handle this scenario more gracefully? In my opinion, the simulator should just exit with error and dump of the internal registers of the simulated processor.
Thank you!
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