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Add support for multiple black-boxed macros (#43)
* Added logging to `fault jtag` simulations * New flags * `--blackbox` names of modules (not instances) inside the design to be blackboxed (i.e. connections treated as outputs or inputs to the circuit): Added to `chain`, `cut` * `--blackboxModels`: Verilog files containing behavioral models for black-boxed instances for simulation: Added to `chain`, `jtag` and must be readable by Pyverilog (sorry) * `--output-fault-points`: Outputs all detected fault points: Added to `main` * `--output-covered`: Outputs coverage metadata: Added to `main` * Created new element, `Module`, which captures and stores metadata about modules * Rewrote simulation scripts to use an array of `models` instead of separate `cells` and `includes` * Rewrote major parts of `fault chain` to support multiple macros (and general code quality) * Fixed a bug where `fault asm` did not load some input names correctly ## Testing * Added new design, `TripleDelay`, to test the use of macros
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