locore: Set CPTR_EL2 before using any Morello instructions

This was a regression in the merge of the VHE changes which moved the
setting of VBAR_EL2 before CPTR_EL2.

sys/arm64/arm64/locore.S

@@ -568,11 +568,28 @@ LENTRY(enter_kernel_el)
 #else
 	mov	x2, xzr /* CPTR_EL2 is managed by vfp.c */
 #endif
+	msr	cptr_el2, x2
+#if __has_feature(capabilities)
+	/*
+	 * Wait for the write to cptr_el2 to complete. It will enable the
+	 * use of capabilities at EL2 that we need below. When not using
+	 * capabilities this is unneeded as the eret instruction will
+	 * act as in place of this barrier.
+	 */
+	isb
+#endif
+
 	ldr	x3, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN)
 	ldr	x5, =(PSR_DAIF | PSR_M_EL2h)
 	b	.Ldone_vhe
 
 .Lno_vhe:
+	ldr	x2, =(CPTR_RES1)
+	msr	cptr_el2, x2
+#if __has_feature(capabilities)
+	isb
+#endif
+
 	/* Hypervisor trap functions */
 	adrp	x2, hyp_stub_vectors
 	add	x2, x2, :lo12:hyp_stub_vectors
@@ -583,23 +600,9 @@ LENTRY(enter_kernel_el)
 	msr	vbar_el2, x2
 #endif
 
-	ldr	x2, =(CPTR_RES1)
 	ldr	x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
 	ldr	x5, =(PSR_DAIF | PSR_M_EL1h)
-
 .Ldone_vhe:
-
-	msr	cptr_el2, x2
-#if __has_feature(capabilities)
-	/*
-	 * Wait for the write to cptr_el2 to complete. It will enable the
-	 * use of capabilities at EL2 that we need below. When not using
-	 * capabilities this is unneeded as the eret instruction will
-	 * act as in place of this barrier.
-	 */
-	isb
-#endif
-
 	/* Enable access to the physical timers at EL1 */
 	msr	cnthctl_el2, x3
 	/* Set the return PSTATE */